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Simulation Based Security Verification

Radix-S employs patented technology to detect and prevent security vulnerabilities in FPGAs, ASICs, and SoCs by leveraging existing verification environments. Its advanced analysis helps security and verification teams identify and isolate security vulnerabilities before the device is manufactured saving costly design re-spins or catastrophic system failure due to an attack.

Hardware security vulnerabilities can be introduced at all stages of the design lifecycle, and fall into the following three major categories:

  • Block-Level Hardware Vulnerabilities: Security bugs that exist even when the IP is analyzed in isolation.
  • System Integration Security Issues: Vulnerabilities can arise due to complex interaction between different IP even if the individual IP is vulnerability-free. Many IP blocks are highly parametrizable and configurable leading to an exponential number of configuration combinations, where a subset may be insecure.
  • Software Configuration and Usage Errors: The effectiveness of many hardware security features relies on the correct software programming. Mistakes in programming can lead to sensitive information being disclosed or modified.

Radix-S incorporates three core technologies to enable pre-silicon security specification and verification at block, subsystem, and chip level.

  • Security rules centered around information flow concepts (ex. confidentiality and integrity) to be efficiently captured.
  • Automated Security Model Design (SMD) generation: automatically generated information flow in synthesizable Verilog RTL capable of checking if rules hold during simulation of the design using existing verification infrastructure.
  • Analysis Views: The Radix Analysis Views displays both signal values and leakage information to identify the source of the vulnerability and the signal values that caused it.

Using Radix-S greatly speeds up your existing RTL security review while diminishing the risk of a hardware security vulnerability making its way into the chip or worse, the final system deployment.

Radix-S is compatible with Cadence® Xcelium™, Mentor® Questa®, and Synopsys® VCS® simulators.

To learn more, download the
Radix-S datasheet