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Emulation Based Security Verification

For today’s complex SoCs, firmware security verification is a tedious manual process that may not adequately identify vulnerabilities directly associated with the hardware, where the majority of exploits can and do occur. While teams may run emulation as part of their verification methodology to ensure their firmware is operating correctly, emulation alone is not sufficient to find and detect security vulnerabilities.

Radix-M provides SoC system level hardware security verification leveraging commercial emulators for firmware and hardware security validation. By running firmware and software on the SoC, Radix-M simultaneously analyzes the entire system, which greatly increases the detection and prevention of security vulnerabilities that may be lurking in the system’s Root of Trust or processing system.

The inputs to Radix-M include System IP or SoC’s RTL files, a set of security rules based on the threat models defined for the system, along with the block or system level testbench files that verification teams are already developing. Radix-M then creates and adds a hardware Security Model to the design. The Security Model is used to check the validity of the security rules while running in a commercially available emulator, such as Synopsys ZeBu, Mentor Veloce, and Cadence Palladium.

Using Radix-M greatly speeds up existing RTL security review while diminishing the risk of a hardware security vulnerability. Radix-M is compatible with Cadence® Palladium® Z1 Enterprise Emulation Platform. For early access availability on Mentor® Veloce® or Synopsys® ZeBu®, please consult your local sales representative.

To learn more, download the
Radix-m datasheet