The security of the U.S. microelectronic designs and their supply chain is becoming a significantly growing concern for both commercial semiconductor companies and the Department of Defense (DoD).  The industry has seen significant impact from both silicon shortages and vulnerabilities that have caused disruption in the assurance of microelectronics that power our autonomous vehicles, 5G, and countless IoT applications. Providing infrastructure for rapid prototyping and development of secure, cutting-edge microelectronics in the U.S. using the latest commercial technologies is critical to the design, manufacture, and delivery of silicon with the highest levels of security assurance. 

To address this, the DoD just announced the award of the Rapid Assured Microelectronics Prototypes using Advanced Commercial Capabilities (RAMP) Phase II program to Microsoft, focused on bringing critical microelectronic infrastructure to the U.S. using commercially available cloud environments provided by Microsoft Azure. RAMP is a critical initiative that will enable the DoD to accelerate the pace of microelectronics innovation by leveraging a more secure and scalable supply chain. A core component of the RAMP Phase II program is for Microsoft to provide a secure silicon design environment on Azure to help develop innovative microelectronic designs with quantifiable assurance.

Over the years, we have worked closely with our defense industrial base (DIB), commercial semiconductor, and electronic design automation (EDA) partners to enable systematic security verification with our Radix software to identify silicon vulnerabilities early in their development. We are now very honored to have Radix included as part of this program to enable quantifiable security assurance throughout the design process. 

Radix is applied in lockstep with chip design, allowing security vulnerabilities to be cost-effectively remediated as they are found, throughout the design and development process. Radix adds systematic hardware vulnerability detection and prevention to existing ASIC, SoC, and FPGA verification methodologies using its comprehensive information flow analysis technology. By bringing more precise and more systematic security practices to every step of the development process, Radix helps to efficiently identify and remediate hardware security vulnerabilities and provides for oversight and governance to confirm security signoff before manufacturing.

Throughout the program, Tortuga Logic will work closely with other technology partners to execute our Radix software on their selected designs to systematically identify any potential weaknesses and provide quantifiable assurance that existing weaknesses are properly mitigated. All work will be performed using Microsoft’s Azure Government Cloud to ensure the confidentiality and integrity of the selected designs and analysis are protected.

We are very much looking forward to supporting Microsoft and the other participating microelectronic industry partners throughout this program to enable this innovative secure design environment for building assurance into our next-generation microelectronics. 


  • Dr. Jason Oberg is a co-founder and Chief Technology Officer (CTO) of Tortuga Logic, where he is responsible for overseeing the company’s technology and strategic positioning. Dr. Oberg works closely with Tortuga Logic’s executive management team, engineering teams, and customers to drive the company’s next-generation hardware security products. Dr. Oberg brings years of deep hardware security expertise, has facilitated the development of several hardware security products, and is a member of the Common Attack Pattern Enumeration and Classification (CAPEC) and Common Weaknesses Enumeration (CWE) board. His work has been cited over 1000 times and he holds seven issued and pending patents. Prior to his CTO role, Dr. Oberg led Tortuga Logic as co-founder and CEO from 2014 – 2020 where he facilitated raising capital, recruiting the initial team, and drove the company’s product revenue growth YoY. He received his B.S. in Computer Engineering from UC Santa Barbara and an M.S. and Ph.D. in Computer Science from UC San Diego.