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ARC Processor System
Security Analysis

Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare® ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities. Tortuga Logic and Synopsys have created and verified security rules, based on common threat models related to both hardware and software misconfigurations of security features of ARC processors.

John Koeter


DesignWare ARC Processor IP provides a rich set of security options that help protect systems from evolving security threats such as IP theft and malicious attacks. When integrating an ARC Processor and adding application software, designers must ensure that the resulting end system remains secure. Tortuga Logic’s Radix-S software is an effective tool for our customers to verify that no vulnerabilities are introduced during the integration and programming of their ARC Processor-based systems.

John Koeter

Vice President of Marketing for IP at Synopsys

Radix-S ARC
Analysis examples:

The ARC debug mode provides increased controllability and observability for both hardware and software testing; however, access to design internals poses a security risk. To ensure debug functionality can only be accessed by authorized users, ARC processors provide the option to configure secure debug features, including a locking/unlocking mechanism. Synopsys provides an example unlock module based on a simple challenge response protocol. Designers however, typically replace the example and define custom unlock logic to provide the security necessary to address specific threat models or to integrate the processor secure debug into a larger SoC secure debug design. This can initiate risk in the hardware.

To learn more download the Radix-S data sheet
and the ARC white paper